Selective deposition method to form air gaps

ABSTRACT

A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of, and claims priority to and thebenefit of, U.S. patent application Ser. No. 15/836,547, filed on Dec.8, 2017 and entitled “SELECTIVE DEPOSITION METHOD TO FORM AIR GAPS,”which is a continuation of, and claims priority to and the benefit of,U.S. patent application Ser. No. 15/205,890, now U.S. Pat. No.9,859,151, filed on Jul. 8, 2016 and entitled “SELECTIVE FILM DEPOSITIONMETHOD TO FORM AIR GAPS,” both of which are incorporated herein byreference.

FIELD OF INVENTION

The present disclosure generally relates to processes for manufacturingelectronic devices. More particularly, the disclosure relates toselectively forming films through atomic layer deposition (ALD) orchemical vapor deposition (CVD). Specifically, the disclosure disclosesmethods to form ALD or CVD films that can be used to form an air gap.

BACKGROUND OF THE DISCLOSURE

Generally, deposition of films has taken place in a manner such thatlayers are grown from the bottom in an upward direction. For example, afilm grown on a wafer is often grown in a direction vertical to thewafer's surface. Other films may be grown vertically on a microstructuresurface. Some examples of features created in this manner include trenchfilling, step formation, or FinFET features, for example.

Air gaps are features with applicability in film deposition. U.S. Pat.No. 7,304,388 to Dubin et al. discloses air gaps that are created byfirst forming a sacrificial interlayer dielectric and decomposing it.The formation may involve an etching step, which may cause problems anddecrease the performance of the device. The formation may also involve adeposition step for protecting liners, metal or metallic surfaces, thusdecreasing the size of the air gap and the performance of the device.For example, International Publication No. WO 2013/101096 to Fischerdiscloses air gap formation with a hood layer. The air gap formation mayalso include an etching step. Air gaps may be used both in back end ofline (BEOL) processing or front end of line processing. Two examples ofapplications for air gaps include air gaps in metallization, such as Cumetallization, or air gaps in NAND memories.

As a result, a method for selectively forming an air gap through ALD orCVD processes resulting in increased performance is desired.

SUMMARY OF THE DISCLOSURE

In accordance with at least one embodiment of the invention, a method offorming an air gap for a semiconductor device through selectivedeposition is disclosed. The method comprises: providing a substrate forprocessing in a reaction chamber; providing a first surface forselectively depositing a film, wherein at least a part of the firstsurface is substantially vertical; and selectively depositing a filmthrough a deposition method on the first surface in at least ahorizontal direction, the film not being deposited on a second surface,wherein the second surface differs from the first surface; whereinselectively depositing the film defines in part an air gap.

For purposes of summarizing the invention and the advantages achievedover the prior art, certain objects and advantages of the invention havebeen described herein above. Of course, it is to be understood that notnecessarily all such objects or advantages may be achieved in accordancewith any particular embodiment of the invention. Thus, for example,those skilled in the art will recognize that the invention may beembodied or carried out in a manner that achieves or optimizes oneadvantage or group of advantages as taught or suggested herein withoutnecessarily achieving other objects or advantages as may be taught orsuggested herein.

All of these embodiments are intended to be within the scope of theinvention herein disclosed. These and other embodiments will becomereadily apparent to those skilled in the art from the following detaileddescription of certain embodiments having reference to the attachedfigures, the invention not being limited to any particular embodiment(s)disclosed.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

These and other features, aspects, and advantages of the inventiondisclosed herein are described below with reference to the drawings ofcertain embodiments, which are intended to illustrate and not to limitthe invention.

FIG. 1 is a perspective view of a semiconductor device in accordancewith at least one embodiment of the invention.

FIGS. 2A and 2B are cross-sectional views of a semiconductor device inaccordance with at least one embodiment of the invention.

FIGS. 3A, 3B, 3C and 3D are cross-sectional views of a semiconductordevice in accordance with at least one embodiment of the invention.

FIGS. 4A, 4B, 4C and 4D are cross-sectional views in accordance with atleast one embodiment of the invention.

FIG. 5 is a cross-sectional view in accordance with at least oneembodiment of the invention.

It will be appreciated that elements in the figures are illustrated forsimplicity and clarity and have not necessarily been drawn to scale. Forexample, the dimensions of some of the elements in the figures may beexaggerated relative to other elements to help improve understanding ofillustrated embodiments of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Although certain embodiments and examples are disclosed below, it willbe understood by those in the art that the invention extends beyond thespecifically disclosed embodiments and/or uses of the invention andobvious modifications and equivalents thereof. Thus, it is intended thatthe scope of the invention disclosed should not be limited by theparticular disclosed embodiments described below.

Selective deposition is desirable in order to grow particular featuresfor a variety of applications. One particular feature, air gaps, hasbeen used in 14 nm nodes, which currently is the smallest node sizemanufactured. Air gaps created in the 14 nm node may have, for example,a height of approximately 140 nm and a width of approximately 50 nm.This gap can be formed in a trench of approximately 180 nm in height,the trench herein meaning the space in between the metallization lines.The area of the air gap may be approximately 6,500 nm², while the trenchcan have an area of 19,700 nm². The volume of the air gap could be inthe range of 1,625,000-32,500,000 nm³, while the trench could have avolume of 4,925,000-98,500,000 nm³. The air gap can be approximately 33%of the size of the trench.

Embodiments according to the invention can result in a larger air gap inthat it can be a greater percentage of the trench, such as 50-60%, forexample. The size of the air gap may be more than about 35%, more thanabout 45%, more than about 50%, more than about 60%, more than about70%, or more than about 80% of the size of the trench or the spacebetween the metallization lines.

One of ordinary skill in the art would understand that different sizesfor the air gap may be possible. For example, the height of the air gapmay range between about 10 to about 500 nm, between about 20 to about300 nm, between about 30 to about 200 nm. Also, the width of the air gapmay range between about 5 to about 250 nm, preferably between about 10to about 200 nm, or more preferably between about 20 to about 100 nm.Also, the width of the air gap may be less than about 50 nm, less thanabout 30 nm, less than about 20 nm or in some instances less than toabout 10 nm. The width can be considered to be measured to a directionof the smaller dimension between the features, for example, the widthbetween metallization lines, the longest dimension of the metallizationlines being cross-sectional to width (i.e., the smaller dimension).

From this, the cross-sectional area of the air gap may range between50-125,000 nm², preferably between about 100 to about 50,000 nm², ormore preferably between about 200 to about 20,000 nm². Thecross-sectional area of the air gap herein can be considered to be across-sectional area of the air gap between the features of device. Thearea can be considered to be measured to a direction of the smallestdimension between the features, for example, the area betweenmetallization lines, the longest dimension of the metallization linesbeing cross-sectional to the area. Furthermore, the size of the air gapin relation to the trench size may range between about 30-80%. Also, thevolume of the air gap could be in the range from about 2,500 to about5,000,000,000 nm³, preferably from about 10,000 to about 500,000,000nm³, or more preferably from about 50,000 to about 50,000,000 nm³.

FIG. 1 is schematic and simplified for the purpose of illustrating theexemplary dimensions. FIG. 1 illustrates a semiconductor device 10 inaccordance with at least one embodiment of the invention. Thesemiconductor device 10 comprises a first metallization line 20 and asecond metallization line 30. The first metallization line 20 and thesecond metallization line 30 may comprise a material, such as copper orother appropriate metal. A gap may exist between the first metallizationline 20 and the second metallization line 30. The gap may have a length40, a height 50, and a width 60. In some embodiments, the air gap may beformed inside the gap and it may have a length, a height, and a widthsmaller than the length 40, the height 50, and the width 60 illustratedin the FIG. 1. In some embodiments, the cross-sectional area of the airgap may be measured or calculated by using the height and the width, ofwhich directions are the same than height 50 and width 60 of the air gapformed inside the gap. In some embodiments, the width 60 may beconsidered to be the smallest or smaller dimension between the features.In some embodiments, the height 50 may be considered to be the smallestor smaller dimension between the features.

Advantages gained from a larger air gap may include improvedperformance, and reducing the effective k-value of the material inbetween the lines. For example, the dielectric constant of low-kmaterials may be approximately 2.52, but the dielectric constant of airis 1. Reduction of the dielectric constant through replacement of thelow-k material with air reduces the Resistive-capacitive (RC) delay. Inaddition, the replacement may result in increased processing speed, useof less current, and reduction of operating temperature and parasiticresistance. In some embodiments, the structure having air gap may have aperformance similar to a material with a k-value of less than about 3.9,less than about 3.6, less than about 3.3, less than about 3, less thanabout 2.7, less than about 2.5, and in some instances, the k-value couldbe less than about 2.3 or even less than about 2.0 when the materialwould be considered to replace the air gap.

Figures presented herein are simplified and do not necessarilyillustrate all layers, structures or features of the exemplaryintegrated circuits or structures that can form part on an integratedcircuit.

FIG. 2A illustrates a semiconductor device 100 in accordance with atleast one embodiment of the invention. The semiconductor device 100 mayinclude a wafer 110, a first layer 120, a second layer 130, and acapping layer 140. The wafer 110 may comprise semiconductor material,such as silicon, silicon germanium or compound semiconductors such asIII-V or II-VI materials. The first layer 120 may be a metal layer ontop of the wafer 110, and may comprise metal or metallic materials, suchas copper or insulating or dielectric material, such as silicon dioxidebased materials or low-k materials. In some embodiments, the first layer120 may comprise silicon and oxygen, for example, silicon dioxide. Insome embodiments, the first layer 120 may not comprise metal. In someembodiments, the first layer 120 may comprise semi-metal material.Additional layers may exist between the first layer 120 and thesubstrate 110; for example, there may be multiple metallization layersor transistor layers or contact layers disposed between the first layer120 and the substrate 110. The second layer 130 may be formed on thefirst layer 120, and may comprise materials comprising metal, such asaluminum nitride tungsten, tungsten oxide or other metallic, metal orinsulating material. In some instances, the second layer 130 may be of adifferent material than the first layer 120. In some embodiments, thesecond layer 130 may comprise a metal or metallic surface. In someembodiments, the second layer 130 may not comprise a semi-metal. In someembodiments, the second layer 130 may comprise metal and oxygen, such asmetal oxide.

The capping layer 140 may be formed on the second layer 130 and maycomprise silicon-based material, such as silicon dioxide, siliconnitride or mixtures thereof. The capping layer 140 may cover portions ofthe second layer 130, leaving a particular portion of the second layer130 exposed. The capping layer 140 may be made of the same material asthe first layer 120. In some embodiments, the capping layer 140 maycomprise silicon and oxygen, for example, silicon dioxide. In someembodiments, the capping layer 140 may not comprise metal. In someembodiments, the capping layer 140 may comprise a semi-metal. It is onthe exposed portion (e.g., a surface or vertical portion 135) of thesecond layer 130 on which selective deposition may take place.

FIG. 2B illustrates the semiconductor device 100 in accordance with atleast one embodiment of the invention. Upon an exposed portion of thesecond layer 130 (e.g., surface 135), a film 150 is depositedsubstantially horizontally along a direction 160 via deposition method,such as ALD, CVD (e.g., cyclic or sequential CVD), or any other suitablechemical and vapor phase based deposition method resulting in selectivedeposition. The film 150 deposited may comprise an insulating ordielectric material (for example, silicon oxide (SiO₂)), metal oxidematerials, transition metal oxides (for example, niobium oxide (Nb₂O₅)),or another low-k material.

For a film 150 formed of metal oxide, the following process may be used.First a surface (e.g., surface 135) to deposit the film 150 on may beprovided. Second, a pulsing step of a metal precursor such as metalhalide, may take place. An example of a metal halide may be a transitionmetal halide, such as niobium fluoride, niobium chloride, tantalumfluoride, tantalum chloride, molybdenum fluoride, molybdenum chloride,tungsten fluoride, tungsten fluoride, vanadium fluoride, vanadiumchloride, chromium fluoride, or chromium chloride. In some embodiments,the metal halide may be NbCl₅ or TaCl₅. The pulsing step may have atemperature ranging between 20 and 600° C., preferably between 100 and500° C., preferably between 150 and 400° C., and preferably between 175and 375° C. The pulsing step may have a duration ranging between 0.01and 120 seconds, preferably between 0.025 and 20 seconds, preferablybetween 0.05 and 10 seconds, and preferably between 0.1 and 5 seconds.

Third, a pulsing step of an oxygen source, such as water, may take placefor example. Other oxygen sources may include oxygen (O₂), ozone (O₃),hydrogen peroxide (H₂O₂), atomic oxygen (O), oxygen radicals, or oxygenplasma, among others. The pulsing step may have a temperature rangingbetween 20 and 600° C., preferably between 100 and 500° C., preferablybetween 150 and 400° C., and preferably between 175 and 375° C. Thepulsing step may have a duration ranging between 0.01 and 120 seconds,preferably between 0.025 and 20 seconds, preferably between 0.05 and 10seconds, and preferably between 0.1 and 5 seconds.

After the pulsing steps, a purging step may take place to expunge anyexcess precursor. In addition, the pulsing steps may be repeated to forma film of a desired thickness.

FIG. 3A illustrates a semiconductor device 200 in accordance with atleast one embodiment of the invention. The semiconductor device 200includes a wafer 210 and a first column comprising a first layer 220comprising a first surface 225, a second layer 230 comprising a secondsurface 235, and a capping layer 240 comprising a third surface 245. Thesemiconductor device 200 may also include a second column comprising afirst layer 220′ comprising a fourth surface 225′, a second layer 230′comprising a fifth surface 235′, and a capping layer 240′ comprising asixth surface 245′. Surfaces 225, 235, 245, 225′, 235′, and 245′ can bevertical portions or comprise vertical portions. The wafer 210 maycomprise silicon, silicon germanium, or another III-V material. Thefirst layer 220 and the first layer 220′ may be a metal layer on top ofthe wafer 210, and may comprise copper or tungsten, for example.Additional layers may exist between the first layers 220 and 220′ andthe substrate 210; for example, there may be multiple metallizationlayers disposed between the first layers 220 and 220′ and the substrate210. The second layer 230 and the second layer 230′ may be formed on thefirst layer 220 and the first layer 220′, and may comprise aluminumnitride, silicon nitride (SiN), or silicon carbon nitride (SiCN).

The capping layer 240 and the capping layer 240′ may be formed on thesecond layer 230 and the second layer 230′. The capping layer 240 andthe capping layer 240′ may comprise silicon oxide, niobium oxide(Nb₂O₅), or another low-k material. The capping layer 240 and thecapping layer 230′ may cover portions of the second layer 230 and thesecond layer 230′, leaving a particular portion exposed (e.g., surfaces235, 235′). It is on the exposed portion (e.g., surface 235, 235′) ofthe second layer 230 and the second layer 230′ on which selectivedeposition may take place.

FIG. 3B illustrates the semiconductor device 200A, which includesstructure 200, in accordance with at least one embodiment of theinvention. Upon an exposed portion (e.g., surfaces 235, 235′) of thesecond layer 230 and the second layer 230′, a film 250 and a film 250′are deposited substantially horizontally via deposition method, such asALD, CVD, or any other suitable deposition method resulting in selectivedeposition. The film 250 deposited may comprise silicon oxide (SiO₂),niobium oxide (Nb₂O₅), or another low-k material. The steps to form thefilm 250, 250′ may be similar to those described in relation to FIG. 2B.

FIG. 3C illustrates a semiconductor device 200B, formed from structure200A, in accordance with at least one embodiment of the invention. Asthe substantially horizontal deposition takes place, a film 250 (mergedwith film 250′) may be formed to bridge the first column with the secondcolumn. A shape of the film 250 may be narrower in the middle due tocrystalline alignment or due to deposition process itself. For example,before closing of the gap 250, there may be only a narrow pathway fromthe air gap to outside environment, which may be difficult to purge inreasonable time before the next precursor pulse. Without being bound toany theory, it may cause some CVD reactions to take place on and aroundthe narrow pathway and it may cause closing of the gap and affect theshape of the film 250. However, other shapes for the film 250 arepossible, including spherical or semispherical.

FIG. 3D illustrates a semiconductor device 200C in accordance with atleast one embodiment of the invention. The first layer 220 may have aliner 225, while the first layer 220′ may have a liner 225′. The liner225 and the liner 225′ may comprise titanium nitride (TiN), tantalumnitride (TaN), tungsten nitride (WN), tungsten (W), tantalum (Ta),titanium (Ti), or other appropriate metallic material. The liner 225 andthe liner 225′ may generally have the features of good conductivity,effective barrier properties, and good adhesion. Surfaces 225, 225′ maycomprise the liner material. As a result of the horizontal deposition,an air gap 260 may be formed. The air gap 260 serves as a replacementfor a low-k dielectric material that would have been in its place.

FIG. 4A illustrates a semiconductor device 300 in accordance with atleast one embodiment of the invention. The semiconductor device 300includes a wafer 310. The wafer 310 may comprise silicon, silicongermanium, or other III-V materials. Disposed on the wafer 310 are aplurality of first layers 320, 320′, and 320″. The first layers 320,320′, and 320″ may comprise copper, tungsten, tantalum, or titanium, forexample, and may be metallization lines in an integrated circuit. Firstlayer 320 can include a first surface 340 and a first substantiallyvertical portion 342, first layer 320″ can include a third surface 340″and a third substantially vertical portion 346, and first layer 320′ caninclude a fifth surface 340′. Covering a portion of the first layers320, 320′, and 320″ (e.g., a portion of first surface 340, a portion ofthird surface 340″, and a portion of fifth surface 340′) are a pluralityof liners 325, 325′, and 325″. The liners 325, 325′, and 325″ maycomprise titanium nitride (TiN), tantalum nitride (TaN), tungstennitride (WN), tungsten (W), tantalum (Ta), titanium (Ti), or otherappropriate metallic material.

A plurality of second layers 330, 330′, and 330″ may be formed on thefirst layers 320, 320′, and 330″. The second layers 330, 330′, and 330″may comprise aluminum nitride, silicon nitride (SiN), or silicon carbonnitride (SiCN), for example. Second layer 330 can include a secondsurface 345 and a second substantially vertical portion 344, secondlayer 330″ can include a fourth surface 345″ and a fourth substantiallyvertical portion 348, and second layer 330′ can include a sixth surface345′.

FIG. 4B illustrates the semiconductor device 300A in accordance with atleast one embodiment of the invention. A portion (e.g., surfaces 335,335′, and 335′, which can comprise vertical portions) of the firstlayers 320, 320′, and 320″ is not covered by the liners 325, 325′, and325″ and the second layers 330, 330′, and 330″. It is on this exposedportion of the first layers 320, 320′ and 320″ that a plurality of films340 may be formed. The plurality of films 340 may be formed through ALD,CVD, or any other suitable deposition method resulting in selectivedeposition.

The films 340 may comprise silicon oxide (SiO₂), niobium oxide (Nb₂O₅),or another low-k material. The steps to form the film 340 may be similarto those described in relation to FIGS. 1B and 2B. The selectivedeposition takes place such that the film 340 forms on the exposedportions of the first layers 320, and 320′, and 320″. The film 340 wouldnot form on the liners 325, 325′, and 325″ or the second layers 330,330′, and 330″.

FIG. 4C illustrates the semiconductor device 300B in accordance with atleast one embodiment of the invention. The films 340 may grow to a pointthat it covers all of the exposed portions of the first layers 320,320′, and 320″. The film 340 may first be grown in a conformal manner,but then grow in a non-conformal manner close to a surface of an openingof the trench or a space between the column stacks. The trench may beclosed by the film 340 by a varying degree. For example, a percentageclosure of the trench by the film 340 may be more than about 20%, morethan about 40%, more than about 60%, or more than about 80%. Such may bealso reflected by the amount of the film 340 deposited. For example, thefilm 340 may comprise more than about 1 nm of deposition, more thanabout 3 nm of deposition, more than about 5 nm of deposition, more thanabout 10 nm of deposition, or more than about 20 nm of deposition.

FIG. 4D illustrates the semiconductor device 300C in accordance with atleast one embodiment of the invention. After the film 340 is formed, afirst dielectric layer 350 and a second dielectric layer 350′ may beformed through a CVD process with parameters resulting in anon-conformal film growth, such as non-conformal plasma enhancedchemical vapor deposition (PECVD) of a silicon oxide-based material, forexample. The first dielectric layer 350 and the second dielectric layer350′ may comprise silicon based materials such as silicon dioxide(SiO₂), silicon carbonitride (SiCN), or a low-k material, for example.The first dielectric layer 350 and the second dielectric layer 350′ maybe formed to create a first air gap 360 and a second air gap 360′. Inaddition, the dielectric layers 350 and 350′ may be formed on the top ofthe second layers 330, 330′, and 330″.

As shown in FIG. 4D, multiple air gaps may be formed between formedstacked layers. Gaps may be less than 200 nm, preferably less than 100nm, more preferably less than 75 nm, and more preferably less than 50nm. A smaller gap may be preferred as being better for ALD processing.In some embodiments, CVD processing may also be applied. By increasingthe empty space of the air gaps, improved performance of the device mayresult.

As mentioned above, the selectivity may be expressed as the ratio ofmaterial formed on the first surface (A) minus the amount of materialformed on the second surface (B) to amount of material formed on thefirst surface (A) (i.e., selectivity can be given as a percentagecalculated by [(deposition on first surface)−(deposition on secondsurface)]/(deposition on the first surface) or [(A−B)/A]). Preferably,the selectivity may be above about 50%, above about 70%, above about80%, above about 90%, above about 95%, above about 98%, above about 99%or about 100%. In some cases, selectivity above 80% may be acceptablefor certain applications. In some cases, selectivity above 50% may beacceptable for certain applications. In some embodiments, the depositiontemperature may be selected such that the selectivity is above about95%. In some embodiments, the deposition temperature may be selectedsuch that a selectivity of about 100% is achieved.

In some embodiments the thickness of the film that is selectivelydeposited is less than about 500 nm, less than about 250 nm, less thanabout 100 nm, less than about 50 nm or less than about 25 nm. In someembodiments, the thickness of the film that is selectively deposited mayrange from about 3 nm to about 200 nm or from about 5 nm to about 50 nm.However, in some cases a desired level of selectivity, for example morethan 80%, or more than 90%, is achieved with the thicknesses of theselectively deposited film being over about 5 nm, over about 10 nm, overabout 15 nm or over about 20 nm.

In some embodiments described above, one or more pretreatment and/orpassivation processes or treatments of one or more of the surfaces ofthe substrate may be performed before selectively depositing the film.Passivation or pretreatments may enhance the selectivity and the growthon the desired surface and may decrease or block, in some instancesalmost completely block the growth on another surface. FIG. 5illustrates such a structure in accordance with at least one embodimentof the invention. The structure may comprise a substrate 410, upon whicha first column comprising a first layer 420 comprising a first surfacecomprising a first vertical portion 425 and a second layer 430comprising a second surface comprising a second vertical portion 430 anda second column comprising a first layer 420′ comprising a third surfacecomprising a third vertical portion and a second layer 430′ comprising afourth surface comprising a fourth vertical portion is formed. The firstlayer 420 and the first layer 420′ may be subject to a pre-treatment orpassivation step prior to the formation of a horizontal selective film440. Once the formation of the horizontal selective film 440 iscomplete, an air gap 450 may be formed.

The particular implementations shown and described are illustrative ofthe invention and its best mode and are not intended to otherwise limitthe scope of the aspects and implementations in any way. Indeed, for thesake of brevity, conventional manufacturing, connection, preparation,and other functional aspects of the system may not be described indetail. Furthermore, the connecting lines shown in the various figuresare intended to represent exemplary functional relationships and/orphysical couplings between the various elements. Many alternative oradditional functional relationship or physical connections may bepresent in the practical system, and/or may be absent in someembodiments.

It is to be understood that the configurations and/or approachesdescribed herein are exemplary in nature, and that these specificembodiments or examples are not to be considered in a limiting sense,because numerous variations are possible. The specific routines ormethods described herein may represent one or more of any number ofprocessing strategies. Thus, the various acts illustrated may beperformed in the sequence illustrated, in other sequences, or omitted insome cases.

The subject matter of the present disclosure includes all novel andnonobvious combinations and subcombinations of the various processes,systems, and configurations, and other features, functions, acts, and/orproperties disclosed herein, as well as any and all equivalents thereof.

What is claimed is:
 1. A method of forming an air gap for asemiconductor device through selective deposition comprising: providinga substrate for processing in a reaction chamber; forming a firstsurface overlying the substrate for selectively depositing a film,wherein the first surface comprises a first substantially verticalportion; forming a second surface, wherein the second surface comprisesa second substantially vertical portion; and selectively depositing thefilm at least on the first substantially vertical portion of the firstsurface relative to the second substantially vertical portion, wherein aportion of the film at least partially defines the air gap.
 2. Themethod of claim 1, further comprising forming a third surface andforming a fourth surface, wherein the third surface comprises the samematerial as the first surface, wherein the fourth surface comprises thesame material as the second surface, and wherein the deposition isselective on third surface relative to the deposition the fourthsurface.
 3. The method of claim 2, wherein both the third and the fourthsurfaces comprise substantially vertical portions and selectivelydepositing the film comprises deposition on the said first and thirdvertical surfaces.
 4. The method of claim 1, wherein the step ofselectively depositing the film substantially closes the air gap.
 5. Themethod of claim 1, further comprising: forming a dielectric layer atleast on top of the film, wherein the dielectric layer defines a portionof the air gap.
 6. The method of claim 5, wherein the step of formingthe dielectric layer comprises a non-conformal deposition process. 7.The method of claim 2, wherein the step of selectively depositing thefilm is performed such that the film grows horizontally from the firstsubstantially vertical portion toward the third substantially verticalportion.
 8. The method of claim 1, wherein the step of selectivelydepositing the film comprises chemical vapor deposition.
 9. The methodof claim 1, wherein the thickness of the film is greater than 10 nm. 10.The method of claim 1, wherein the selectivity of deposition of the filmon the first substantially vertical portion of the first surfacerelative to the second substantially vertical portion is greater than80%.
 11. The method of claim 1, wherein the air gap is part of anintegrated circuit and has a performance similar to dielectric materialwith k-value of less than 3.6.
 12. The method of claim 1, wherein theair gap is part of an integrated circuit and size of the air gap is morethan 35% of the space between metallization lines.
 13. The method ofclaim 1, wherein the film comprises a low-k material.
 14. The method ofclaim 1, wherein the film comprises an insulating material.
 15. Themethod of claim 1, wherein the first surface comprises metal and thesecond surface comprises silicon.
 16. The method of claim 1, wherein thestep of selectively depositing the film comprises: pulsing a metalhalide precursor on the first substantially vertical surface; pulsing anoxygen precursor on the first substantially vertical surface; andrepeating the pulsing steps until the film grows to a desired thickness.17. The method of claim 16, wherein the metal halide precursor comprisesone or more of NbCl₅ and TaCl₅.
 18. The method of claim 16, wherein theoxygen precursor comprises at least one of: water (H₂O), oxygen (O₂),ozone (O₃), hydrogen peroxide (H₂O₂), atomic oxygen (O), oxygenradicals, and oxygen plasma.
 19. The method of claim 16, wherein atemperature of the reaction chamber ranges between 20 and 600° C. 20.The method of claim 1, wherein a portion of the first surface comprisesa liner.